1. Field of the Invention
This invention relates generally to minicomputer systems and more particularly to storage hierarchies having high speed, low capacity storage devices and lower speed, high capacity storage devices coupled in common to a system bus.
2. Description of the Prior Art
Prior art systems using the round robin type of replacement procedure have the cache store organized in levels. A round robin counter is used to indicate the next level into which replacement information is written. Also, in the prior art a full/empty mechanism is included to indicate the status of the information in each of the levels of the store.
During the initialization operation the prior art systems clear the cache by resetting the full/empty indicators.
In the prior art, the replacement procedure included logic circuitry to assure that valid data was stored in cache since random data might be resident in the cache store on an initialize cycle, for instance.
U.S. Pat. No. 3,840,862 issued to D. T. Ready entitled "Status Indicator Apparatus for Tag Directory in Associative Stores" and U.S. Pat. No. 3,845,474 issued to R. E. Lange, et al., entitled "Cache Store Clearing Operation for a Multiprocessor Mode" both describe such systems.
The disadvantages of the additional storage of the full/empty bits with the complexities of the additional logic circuitry are overcome by the approach used in this invention.